There are many different levels of packages and interconnections in electronic packages. In a typical first level packaging process, a silicon die is joined to a ceramic substrate carrier. In a typical second level packaging process, the ceramic substrate carrier with the die is mounted on an organic board.
In one conventional method for forming a first level package, a passivation layer is formed on a semiconductor die (which may be in a semiconductor wafer). The passivation layer includes apertures that expose conductive regions on the semiconductor die. Titanium and copper layers are sputtered on the upper surface of the conductive regions and the passivation layer. A layer of photoresist is then patterned on the semiconductor die so that the apertures in the patterned photoresist layer are over the conductive regions. Solder is electroplated in the apertures in the photoresist layer until the apertures are filled with solder. The photoresist is stripped and the portions of the titanium and copper layers around the solder deposits are removed. Then, the solder deposits are subjected to a full reflow process. The full reflow process causes the solder deposits to form solder balls. After forming the solder balls, the semiconductor die is bonded face-down to a carrier. The solder balls on the semiconductor die contact conductive regions on the chip carrier. Non-soluble barriers are disposed around the conductive regions and constrain the solder balls. The solder balls between the conductive regions on the carrier and the semiconductor die melt and wet the conductive regions on the carrier. Surface tension prevents the melting solder from completely collapsing and holds the semiconductor die suspended above the carrier.
During the reflow step, the deposited solder substantially deforms into solder balls. Because of the deformation, the heights of the resulting solder balls on the semiconductor die can be uneven. If the heights of the solder balls are uneven, the solder balls may not all contact the conductive regions of the carrier simultaneously when the semiconductor die is mounted to the chip carrier. If this happens, the strength of the formed solder joints may be weak thus potentially decreasing the reliability of the formed package. Moreover, during the reflow process, the deposited solder is exposed to high temperatures for extended periods of time. Excessively heating the deposited solder can promote excessive intermetallic growth in the solder deposits. Intermetallics in the solder joints make the solder joints brittle and reduce the fatigue resistance of the solder joints. Lastly, performing a full reflow process takes time and energy and thus adds to the cost of the die package that is finally produced. If possible, it would be desirable to reduce the time and energy associated with the full reflow process.
One approach to solving the above problems is to use a “stud bumping” technique to form a copper stud on the conductive regions, instead of solder. The copper stud is formed using a wire bonding technique where an end of a wire forms a ball, which is compressed to a conductive region of a semiconductor die. The wire is then cut leaving the compressed ball, which is in the form of a copper stud. The semiconductor die is then flipped over and is then mounted to a carrier of a circuit board having conductive lands with Pb—Sb—Sn solder.
While the described stud bumping approach is feasible, there are some problems to be addressed. First, in the above-described approach, a thick intermetallic compound layer can form between the copper stud and the Pb—Sb—Sn solder. The thick intermetallic compound layer can increase the “on resistance” of the die package. Second, voids can form between the copper in the copper stud and the thick intermetallic compound layer. As shown in FIG. 1, for example, after testing for 1000 hours at 150 ° C., a gap (or void) is shown between a formed intermetallic compound layer and the copper stud. The gap results in a poor electrical and mechanical connection between the semiconductor die and the carrier to which it is attached. Without being bound by theory, the inventors believe that the void formation at the copper/intermetallic compound interface is caused by either copper oxidation and/or the differences in diffusion rates of Cu, Sn, and Sb.
Embodiments of the invention address these and other problems.